Automated logic mapping system

ABSTRACT

NO ABSTRACT AVAILABLE IN THE IFI DATABASE FOR THIS PATENT

"Published at the request of the applicant or owner in accordance withthe Notice of Dec. 16, 1969, 869 0.G. 687. The abstracts oi. DefensivePublication applications are identified by distinctly numbered seriesandare arranged chronologically. The heading of each abstract indicates thenumber of pages of specification, including claims and sheets ofdrawings contained in the application as originally filed. The files 'ofthese applications are available to the public for inspection andreproduction may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to themerits of alleged invention. The Patent and Trademark Ofiice makes noassertion as to the novelty of the disclosed subject matter.

PUBLISHED NOVEMBER 4:, 1975 Thddgllilti AUTQMATED LUGH MAPPENG YTEMPeter H. Oden, 120 Pines Bridge Road, Ossining, N.Y. 10562; Roy L.Russo, 1793 Blossom Court, Yorktown Heights, N.Y. 10598; and Peter K.Woltl, 81"., Glen Road, P.0. Box 426, Shrub Oak, N.Y. 10588 Continuationof application Ser. No. 300,954, Get. 26, 1972. This application May 17,1974, Ser. No. 470,871 Int. (ll. (206? 9/06, 13/00 US. Cl. 444-1 8Sheets Drawing. 34 Pages Specification BLOCK GRAPH 18 2? MAPPHJG J (VGP)(VAP) RESULTS A process for allocating a plurality of block units with apredescribcd interconnection specification, to a plurality of moduleunits. The allocation process may be varied from a partition having azero block redundancy, to a mapping which has some degree of redundancyfor the purpose of minimizing the total number of modules required. Theprocess is applicable to any system wherein interconnected blocksub-units must be assigned to larger module units for organizationalpurposes. For example, the allocation of circuits to chip structures.

In the present invention an automatic process for mapping blocks tomodules is provided. The process consists of a set of programs thatoperate on a given block graph input and provide an output graph whichmay take the form of either a partition or a mapping.

The automated mapping process consists of two major constituents, avertex generation program (VGP) and a vertex allocation program (VAP).Vertex generation is a sub-grouping process to commonly assigninterconnected blocks into a subunit known as a vertex. The programbegins with a list of initiate vertices to which blocks are added untila complete list of vertices is formed. The initiate vertex acts as anucleus from which the vertex is grown. The VGP terminates by outputtinga complete vertex graph that is introduced as input to VAP.

The vertex allocation phase performs a systematic assignment ofverti-ces to modules. VAP structures the input vertex graph into aformat which may be processed to determine which of the vertices may beassigned to a common module. In order to achieve a minimized costmapping, VAP may be used iteratively by the user so as to execute amapping onto a predetermined number of modules in accordance with aplurality of structure and user restrictions.

Nov. 4,. 1975 P. H. ODEN et a1. T940,008

AUTOMATED LOGIC MAPPING SYSTEM Original Filed May 17, 1974 Sheet 1 of 8[INPUT OATA MODE CONTROL 1e VERTEX 26 VERTEX USER INITIATE VERTICES 20GENERATION ALLOCATION BLOCK GRAPH 18 PROCESS 22 V PROCESS MAP/PING (VGP)(W) RESULTS N5 N7 I1 B3 I2 Q B5 01 B1 FIG. 4 M

X N2 9 N5 B2 B4 B6 02 m 1V4 1V6 VER1 N8 I2 B5 01 FIG. 4A N1 B1 i N9\ N552 B4 B6 A 02 I3 1V5 IV? INVENTORS PETER H. ODEN ROY L. RUSSO PETERK.WOLFF, SR BY A? 57m AGENT Nov. 4, 1975 Original Filed AUTOMATED LOGICMay 17, 1974 STA RT P. H. ODEN et a1.

FIG.2A

READ BLOCK CRAPH,MODE CONTROL, INITIATE VERTICES.

VERTEX GENERATION PROCESS (VGP) CENERATE INITIATE VERTICES FOR ALL USERSPECIFIED, INITIATE VERTICES CENERATE AN INITIATE VERTEX FOR EACH BLOCKHAVINCAN OUTPUT NET CONNECTING BLOCKS OF DIFFERENT AREA KINDS.SUCH ASPRIMARY INPUTS AND 0UTPUTS,AND FOR EACH BLOCK WITH NO OUTPUT NETS.

SELECT AN INITIATE VERTEX V ARE ALL INITIATE VERTICES SELECTED? YES PUTTHE INITIATE BLOCKS OFV IN LISTB EXAMINE EACH VERTEX V AND I SET usn.EMPTY SELECTA BLOCK FROM LIST B MAKE EACH INPUT NET TO V AN OUTPUT NETFROM THE FIRST VERTEX CONTAINING THE SOURCE BLOCK FOR THE NET IFNOT AL-READY AN OUTPUT.

ARE ALL BLOCKS SELECTED? VERTEX CRAPH OUTPUT T0 VAP SELECT AN INPUT NETOF THE SELECTED BLOCK ARE ALL INPUT NETS SELECTED YES IS THESELECTED NETAN OUTPUT NET OF ANY BLOCK IN AN INITIATE VERTEX INPUT NET LIST FOR v. A

TO FIC.3A

YES (VAP) FIC.2B

FIG.2

Nov. 4, 1975 P. H. ODEN et a1. T940,008

AUTOMATED LOGIC MAPPING SYSTEM Original Filed May 17, 1974 Sheet 4 of 8FROM FIG. 2A (V.G.P.I

F! 6 3A READ IN FOR EACH VERTEX ITS= A MEMBER BLOCKS VERTEX b) INPUTNETS ALLOCATION OUTPUT NETS PROCESS (VAP) READ IN NUMBER OF MODULES.READ IN AREA OF EACH BLOCK.

READ IN FOREACH MODULE= (1.)MAXIMUM AREA PER MODULE bIMAXIMUM PINS PERMODULE cILIST OF ALLOCABLE VERTICES dIMANUAL ALLOCATIONSPECIFICATION,IFANY.

ALLOCATE VERTICES SPECIFIED TO MODULES SPECIFIED.

DECREASE MODULE PIN AND AREA CAPACITIES TO REFLECT ALLOC- ATION.

DOES AT LEAST ONE MODULE HAVE AN INITIAL ALLOCATION YES NO SELECT ANUNALLOCATED ALLOCABLE VERTEX RANDOMLY.

FIG. ALLOCATE VERTEX TOA RANDOM MODULE 3A FIG. 3B

DECREASE PIN AND AREA CAPACITIES T0 REFLECT ALLOCATION E FIG.3

Nov. 4, 1975 P. H. ODEN et a1. T940,008

AUTOMATED LOGIC MAPPING SYSTEM Original Filed May 17, 1974 Sheet 5 of 8YES CREATE A CANDIDATE VERTEX LIST CONSISTINC OF ALL ALLOCABLE VERTICESWHICH SHARE A NET WITH THE VERTICES THUS FAR ALLOCATED SELECT j'FORSMALLEST Rj- TIES BROKEN ARBITRARILY.

SELECTi' FOR SMALLEST Fij FOR THISj-TIES BROKEN ARBITRARILY.

ALLOCATE VERTEX j' TO MODULE i ALTER PIN AND AREA CAPACITIES ON MODULEAND REMOVE VERLTIESX FROM CANDIDATE ADD UNALLOCATED ALLOCABLE VERTICESTHAT SHARE A NET WITH VERTEXJ'TO CANDIDATE LIST, IF NOT ALREADY THERE.

ARE ALL ALLOCABLE VERTICES ALLOCATED? I Y s o E 'N ALLOCATION ATTEMPT ISSUCCESSFUL; COMPUTE THE AREA Ai j NEEDED IF cANDTDATE SUPPLY MAPPINGRESULTS To VERTEXj WOULD BE ADDED To MODULEi USER OVER ALLI AND T-TERMINATION COMPUTE THE PINS Pij NEEDED IFCANDIDATE VERTEX] WOULD BEADDED TO MODULEi OVER ALL i ANDj.

I SELECT THE NEXT VERTEX MODULEL PAIR ARE ALLij PAIRS SELECTED? NDI YESWILL VERTEXj FIT ON MODULE '1 M YES L Nov. 4, 1975 P. H.,ODEN et a1.T940,008

AUTOMATED LOGIC MAPPING SYSTEM Original Filed May 17, 1974 Sheet 6 of 8WHERE kp,cp, ka ,ca, ARE CONSTANTS.

SELECT NEXT VERTEXJ T0 EXAMINE.

ARE ALL VERTEX] '3 EXAMINED? YES NO D0 ANY RJ'$=0? DOALL Fij'S FOR THISj="K? NO YES NO Rj=-K H was 'AREALLRj'S=K? IS ONLY ONE Fij FURNISH-K? NOYES I no i= ALLOCATION ATTEMPT IS UNSUCCESSFUL; I SUPPLY MAPPINGRESULTSSMALLEST FH TOUSER- NEXTSMALLESTFijFORTHISj TERMINATION ALLOCATE VERTEXWITH LOWESTj AND RJ=0 TO THE MODULE IT FITS 0N Nov. 4, 1975 P. H. ODENet a1.

AUTOMATED LOGIC MAPPING SYSTEM Sheet 7 of 8 Original Filed May 17, 1974MODULE 1 MODULE 2 Nov. 4, 1975 P. H. ODEN et a1. T940,008

AUTOMATED LOGIC MAPPING SYSTEM Original Filed May 17, 1974 Sheet 8 of sAREA PINS MODULE 1 2 1 FIG. 8 MODULE 2 4 4 VER1 IV5 MODULE 1 1 2 PINS PMFIG. 9 MODULE 2 3 4 VER1 1V5 MODULE 1 2 2 AREA AH FIG. 10 MODULE 2 2 3vER1 IV5 VER1 IVS MODULE 1 132 -1 132 144 F11 F11 MODULE 2 156 182 156182 FIG.11A FiG.11B

VER1 IV5 vER1 H5 132 152 MN R T5? 0 R W 182 FIG.12A FIG.12B

